Semiconductor device having a ferroelectric capacitor with a planarized lower electrode

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United States of America Patent

PATENT NO 5382817
SERIAL NO

08020082

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Abstract

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A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion. Therefore, the space between a capacitor upper electrode 316 and platinum layer 314 constituting the capacitor lower electrode can not be made narrow, and an electric field between platinum layer 314 and capacitor upper electrode 316 is made uniform, enhancing pressure-resistant and leakage-resistant characteristics. Also, a silicification reaction of platinum layer 314 is prevented due to plug electrode layer 313. In addition, when plug electrode layer 313 is formed of Ti or TiN, adhesion of plug electrode layer 313 and interlayer insulating film 311 is improved, and thus separation of platinum layer 314 is prevented.

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Patent Owner(s)

Patent OwnerAddress
MITSUBISHI DENKI KABUSHIKI KAISHACHIYODA-KU TOKYO 100-8310

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Itoh, Hiromi Hyogo, JP 22 746
Kashihara, Keiichiro Hyogo, JP 41 659

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