Output buffer circuits including voltage compensation
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United States of America Patent
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-
Jan 17, 1995
Grant Date -
N/A
app pub date -
Feb 25, 1993
filing date -
Feb 27, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Disclosed is an output buffer circuit for allowing a reduction in overshoot and undershoot without a decrease in output speed of an output signal. This output buffer circuit includes a PMOS transistor and an NMOS transistor complementarily connected to each other, an impedance increasing circuit connected in parallel to PMOS transistor, and an impedance increasing circuit connected in parallel to NMOS transistor. Impedance increasing circuit increases output impedance in accordance with an increase in voltage on an output node of a CMOS circuit. Impedance increasing circuit increases output impedance in accordance with a decrease in voltage on output node of the CMOS circuit.
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