Importance

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Abstract

An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A break logic having an arm input is connected to an instruction pointer counter (IP counter). The break logic matches the IP counter to an instruction execution address. A counter is provided that once started runs a period of time and then shuts itself off, the length of the period of time being equal to the amount of time it takes for the break logic to arm after assertion of the arm input. A break logic control is connected to the input pin activates the arm input in response to signals on the input pin. The break logic control also starts the counter. The break logic control includes means connected to the arm input, to the counter, to the match output, and to the abrupt break input, operative upon the condition that the match output is asserted during the period of time, to inhibit the assertion of the arm input by the break logic control and asserts the abrupt break input to the abrupt break logic.

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First Claim