Configuration and method for positioning semiconductor device bond pads using additional process layers
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United States of America Patent
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Jan 24, 1995
Issued Date -
N/A
app pub date -
Oct 3, 1993
filing date -
Jun 15, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor chip (12) includes a plurality of bond pads (16). A plurality of bond shelves (28) are located along opposed end edges (20, 22) of the chip (12). The bond pads (16) are oriented in selected areas remote from the bond shelves (28). A via (42) is formed through an insulating layer (38) to the surface of the bond pad (18) to provide electrical connection thereto. A metallization layer (44) is formed over the an insulating layer (38), filling the via (42). The metallization layer (44) is patterned and etched to form a patten of trace lines (18) spatially separated to connect each bond pad (16) to bond shelves (28).
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