Importance

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Abstract

A switch memory 100 for implementing a multilevel hierarchical routing table in a switch is disclosed. The switch memory 100 includes a plurality of mask circuits 120, 121 and 122, which each correspond to one level of the multilevel hierarchy. Each mask circuit 120, 121 and 122 receives a destination address of an incoming call or packet and masks out portions of the received destination address which do not correspond to the level of the hierarchy with which the mask circuit 120, 121 or 122 is associated. A memory array 130, 131 or 132 corresponding to each mask circuit 120, 121 or 122, is provided which is capable of storing a table of entries including an output port entry and a corresponding destination address of one level of the multilevel hierarchy of destination addresses. Additionally, each memory array 130, 131 or 132 is capable of comparing, in parallel, non-masked portions of the masked destination address outputted from the corresponding mask circuit 120, 121 or 122 with corresponding portions of each destination address of each table entry stored therein. Finally, the switch memory 100 includes a prioritizer 150 for enabling the output of an output port entry of a matched table entry from the memory array 130, 131 or 132, storing destination addresses of the lowest level in the hierarchy, in which a match occurred.

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First Claim