Importance

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Abstract

A reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first mechanism is included for generating the state table and a second mechanism is provided for generating the mode control signals with each transmitted to the reconfigurable state machine mechanism. In a preferred embodiment, an initiation logic device generates and downloads a state table and a plurality of mode control signals to a programmable state machine when the reconfigurable computer interface is utilized to connect a new external peripheral device to a signal processing system. The state table defines the characteristics of the state machine and the state machine controls the operation of the reconfigurable computer interface. The programmable state machine utilizes the present state, the state table and the mode control signals to determine the next machine state which provides rapid and convenient reconfigurability of the interface circuit to connect a variety of external devices to the signal processing system. A bus sizing register circuit is included to modify the word size of a plurality of data signals and temporary memory is also included.

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First Claim