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Abstract

A data processing apparatus and method are described in which a CPU is operable in either a main processing mode (User32) or an exception processing mode (e.g. FIQ32). The CPU has a plurality of main data registers (R0 to R15) and a processing status register (CPSR) for use in the main processing mode. Upon entering the exception processing mode at least one exception data register (R8fiq to R14fiq) is substituted for use in place of a respective corresponding one of the main data registers and the data held within the processing status register is stored within a saved processing status register (SPSRfiq). When the exception processing mode is left, the main data registers are returned for use in place of the exception data registers and the data stored within the saved processing status register is restored to the processing status register. A plurality of exception processing modes are described each having their own associated exception data registers. When a further differing exception occurs within an exception processing mode, the CPU switches to that further differing exception processing mode and uses its own exception data registers and saved processing status register in place of those of the existing processing mode. In this way, nested exception processing is provided.

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First Claim