Importance

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Abstract

A self-timed data pipeline comprised of a plurality of pipeline stages, each one incorporating at least one data latch coupled to selectively configured combinational logic is disclosed. The combinational logic is selectively configured to suit the demands of the particular data pipeline, and provides clocking to the at least one data latch in the pipeline stage. A self-timed data pipeline is thereby readily and inexpensively constructed with combinational logic and logic elements available in commodity application specific integrated circuits. The pipeline stages in the self-timed data pipeline advantageously communicate and pass data in an asynchronous fashion through the use of READY and ACKNOWLEDGE signals.

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First Claim