Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells
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United States of America Patent
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Feb 7, 1995
Grant Date -
N/A
app pub date -
May 5, 1994
filing date -
May 5, 1994
priority date (Note) -
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Abstract
An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.
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