Reconfigurable programmable digital filter architecture useful in communication receiver
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United States of America Patent
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Feb 7, 1995
Grant Date -
N/A
app pub date -
May 6, 1993
filing date -
May 6, 1993
priority date (Note) -
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Abstract
A VLSI integrated circuit, which comprises a single IIR input and global section and identically-structured cascadable filter sections, each of which filter sections includes a pair of time-multiplexed, real-coefficient, input-weighted FIR filter units and additional delay means, can be selectively programmed to operate in any one of a number of different filter configurations that can define real FIR or IIR filters, complex FIR or IIR filters, or filters which are various combinations thereof. One or more of such integrated circuits are useful for implementing a digital deghosting and/or equalization filter.
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