Method and apparatus for placing an integrated circuit chip in a reduced power consumption state
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United States of America Patent
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Feb 7, 1995
Issued Date -
N/A
app pub date -
Apr 26, 1993
filing date -
Mar 6, 1992
priority date (Note) -
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Abstract
A method and apparatus for a chip to monitor its own activity and enter and exit a state of reduced power consumption. The present invention includes defining a predetermined state in which the chip could power down cleanly and monitoring the chip to determine when the chip is in that predetermined state. The present invention also includes a method and apparatus for putting the chip in a state of reduced power consumption state when the chip is in the predetermined state. The present invention also includes a method and apparatus for either turning off the clock generation circuitry or leaving it on during the power down state.
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