System including a data processor, a synchronous dram, a peripheral device, and a system clock
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United States of America Patent
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Feb 14, 1995
Issued Date -
N/A
app pub date -
Jan 21, 1994
filing date -
Apr 23, 1991
priority date (Note) -
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Abstract
A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
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