Test pattern generation
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United States of America Patent
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Feb 14, 1995
Grant Date -
N/A
app pub date -
Oct 28, 1992
filing date -
Oct 28, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).
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