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Abstract

A method and apparatus for remapping of row addresses of memory requests to random access memory. A master device such as a central processing unit (CPU) issues a memory request comprising a memory address to the memory. The memory consists of multiple memory banks, each bank having a plurality of rows of memory elements. Associated with each memory bank is a sense amplifier latch which, in the present invention, functions as a row cache to the memory bank. The memory address issued as part of the memory request is composed of device identification bits to identify the memory bank to access, row bits which identify the row to access, and column address bits which identify the memory element within the row to access. When memory is to be accessed the row of data identified by the row bits is loaded into the sense amplifier latch and then is provided to the requesting master device. When a memory request is issued control logic determines whether the requested row is already located in the sense amplifier latch. If the row is already located in the sense amplifier latch, data is immediately provided to the requesting master device. If the row is not loaded into the sense amplifier latch, the memory bank is first accessed to load the row into the latch prior to providing the data to the requesting master device. As the memory access is faster if the requested row is already located in the latch and memory accesses frequently experience spatial and temporal locality, address remapping is performed to distribute neighboring accesses among the banks of memory. By distributing accesses among the banks of memory, the probability that the requested row is located in a latch in increased and the contention for a single latch is decreased.

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First Claim