Low power dissipation autozeroed comparator circuit
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United States of America Patent
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-
Feb 21, 1995
Grant Date -
N/A
app pub date -
Nov 30, 1992
filing date -
May 30, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A comparator circuit includes a first amplifier stage whose input can be selectively connected to an input voltage and to a reference voltage. A second amplifier stage is connected to the output of the first amplifier and a final stage is connected to the output of the second amplifier stage, at which a rectangular signal is output. The rectangular signal represents times in which the input signal is higher or lower than the reference signal. Both amplifier stages include a first input capacitance having one plate connected to the input of that stage. The other plate of the capacitance is connected to the gate of a transistor and a control switch. Low power dissipation is realized in the circuit by including a follower cascaded with an inverter. This structure allows the same operation as the prior art but offers a better design flexibility since all design parameters are free to be rearranged to achieve the required performance. Furthermore, the switch of the second stage is opened with a delay compared to the opening of the switch of the first stage. This results in lessening the voltage peaks in input capacitor C1 due to the clock feed through charge injection.
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