Tab semiconductor package with cushioned land grid array outer lead bumps

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5394009
SERIAL NO

08099617

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Abstract

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A film of elastomeric material is used to laminate the tape with LGA outer lead bumps to the stiffner plate of the semiconductor package. The elastomeric material has the necessary physical and electrical characteristics to provide the required firmness to maintain good electrical contact between the outer lead bumps and the corresponding contacting pads on a socket, ceramic substrate or PWB, and at the same time, to provide the required resilience to accommodate differences in heights between the outer lead bumps. The stiffner plate is fabricated with a cavity at its center for accommodating the VLSI die, and slots along the outer edges of its underside for storing the excess elastomeric material squeezed out when laminating the tape to the stiffner plate, thereby preventing the excess squeezed out elastomeric material from building up at the outer edges of the semiconductor package to a height in excess of the outer lead bumps. As a result, the land pattern on the socket, ceramic substrate or PWB is not required to address the differences in heights between the outer lead bumps.

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First Claim

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Patent Owner(s)

Patent OwnerAddress
SUN MICROSYSTEMS INC4150 NETWORK CIRCLE SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Loo, Mike C San Jose, CA 10 645

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