Optimized binary adder and comparator having an implicit constant for an input
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United States of America Patent
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Feb 28, 1995
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N/A
app pub date -
Mar 11, 1994
filing date -
Mar 11, 1994
priority date (Note) -
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Abstract
A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or a zero. The three-input comparator can be modified to be a three-input adder by using a full carry-propagate adder (CPA). By taking into account a priori restrictions on the possible input operands, these arithmetic circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.
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