Stable memory circuit using dual ported VRAM with shift registers in a multiple memory bank setup for high speed data-transfer
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United States of America Patent
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Feb 28, 1995
Issued Date -
N/A
app pub date -
Sep 9, 1993
filing date -
Sep 11, 1989
priority date (Note) -
Expired
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Abstract
A stable memory circuit which includes a pair of memory banks (2(a)) and (2(b)) each having eight arrays of eight VRAMs (3). Each VRAM (3) is dual-ported and includes a processor port connected to a processor bus (6) and a stable memory port connected to a stable memory bus (7). Accordingly, stable memory operations such as copying operations may be carried out on the stable memory bus (7) concurrently with conventional random accesses by a host processor via the processor port (6) and with very little use of processor time. Further, the stable memory ports of VRAMs (3) are serial ports and each memory bank (2(a)) and (2(b)) may transfer data at high speed using wide serial data path.
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