Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM
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United States of America Patent
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-
Feb 28, 1995
Issued Date -
N/A
app pub date -
Jul 1, 1994
filing date -
Feb 20, 1992
priority date (Note) -
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Abstract
A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.
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