Wiring arrangement for a semiconductor device using insulating and etch stop layers
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United States of America Patent
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-
Mar 7, 1995
Issued Date -
N/A
app pub date -
Apr 8, 1994
filing date -
Jan 21, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, an etching stopper layer is provided in the oxide layer. A layer already present in the process may be used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.
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