Digital filter circuit that minimizes holding errors transmitted between holding circuits
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United States of America Patent
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-
Mar 7, 1995
Grant Date -
N/A
app pub date -
Nov 23, 1993
filing date -
Nov 24, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.
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