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Abstract

A two-phase sense amplifier includes a data sensing circuitry including a presetting current detecting circuit for allowing the sense amplifier to be in a presetting phase when an X-decoder decodes an address of a selected word line of a selected memory cell and a Y-decoder decodes an address of a selected bit line of the selected memory cell and then for setting a voltage level of the selected bit line to be around a switching point and an evaluating current detecting circuit for allowing the sense amplifier to be in an evaluating phase after the voltage level of the selected bit line is around the switching point in order to sense a current in the selected cell for converting the current into a voltage output, a dummy cell circuitry electrically connected to the data sensing circuitry for providing a reference voltage to the data sensing circuitry, and a differential amplifier electrically connected to the data sensing circuitry and the dummy cell circuitry for accepting and comparing the voltage output and the reference voltage to sense data of the selected memory cell. Such a sense amplifier can have a relatively high sensing speed.

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First Claim