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Abstract

Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus. A virtual bus interface (VBI) receives entries made in the input buffer, whereafter the input buffer is relieved to accept other commands. A cache invalidation queue (CIQ) register stores addresses of cache subblocks to which incoming invalidate operations have been directed. The address of the destination device is also written to the output buffer. If the address of the destination device stored in the output buffer matches the address in the CIQ register, the CC will issue a read-invalidate command, wherein the invalidated block of cache is again filled with data corresponding to the prior-accessing processor, thus invalidating the intervening overwrite issued by the later accessing CPU. Response time to snooping requests is thereby bounded, and data consistency between cache and processor are thereby maintained.

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