Multi-chip semiconductor arrangements using flip chip dies
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United States of America Patent
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Mar 21, 1995
Issued Date -
N/A
app pub date -
Nov 12, 1992
filing date -
Jul 17, 1992
priority date (Note) -
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Abstract
Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.
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