Apparatus for quantizing pixel information to an output video display space

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United States of America Patent

PATENT NO 5402506
SERIAL NO

08265496

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Abstract

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A quantization processor (64) is provided that is operable to provide an error diffusion for adjacent output pixels in an output display space. Three quantization processors (300), (302) and (304) are provided for the three colors of the video RGB format. A full adder (312) is provided for receiving both an error signal and an input pixel value. The composite output is input to an input/output error register 328 that is operable to store bits of the output of the adder, determined to be output bits, and also to store the remainder of the bits that are determined to be error or truncated bits. The error or truncated bits are fed back to the input of the full adder. A rounding decoder (306) is operable to receiving a masking word, such that the outputs from the register (326) are either selected as bits to be truncated, provide an error to be added to the next sequential pixel value, or they are selected as outputs. The register (326) is operable to store the error bits for the next sequential cycle.

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Patent Owner(s)

Patent OwnerAddress
NVIDIA CORPORATION2788 SAN TOMAS EXPRESSWAY SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schafer, John C Wylie, TX 13 451

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