Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 4, 1995
Issued Date -
N/A
app pub date -
Jan 29, 1993
filing date -
Sep 3, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A process for manufacturing a pin grid array package providing a plurality of electrical input and/or output connections using a plurality of stacked, but spaced apart, separate leadframes which are preformed and include a plurality of electrical leads having first and second ends for providing a plurality of different connections. An insulating layer is positioned between adjacent leadframes and the package is bonded together.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully