Importance

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Abstract

A microprocessor system, including a central processing unit (CPU), data source device and data destination device electrically interconnected by first data bus lines, address bus lines and control bus lines of a system bus, is implemented with a transfer signal control line, and second data bus lines interconnecting the data source and data destination devices for direct background transfer of data between the devices. At least one of the devices includes individually sequentially addressable storage locations, and associated address and count registers. The data source device includes 'ready' and 'enable output' terminals, and the data destination device includes 'ready' and 'enable input' terminals, all connected in AND-gate configuration so that the devices are enabled for data transfer through the second data bus lines only when both device 'ready' signals and the transfer control signal are all present. A starting address is loaded in the address register and a total data unit count is loaded in the count register using the first data bus lines. The transfer control signal is then given, with the address and count registers incremented after each data unit is transferred. Once the process is started, data is transferred data unit-by-data unit and without the need for direct CPU involvement, in synchronism with the system clock, until the count register indicates completion of transfer of the entire block.

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First Claim