Memory array of integrated circuits capable of replacing faulty cells with a spare
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United States of America Patent
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Apr 11, 1995
Grant Date -
N/A
app pub date -
Dec 31, 1991
filing date -
Jul 6, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fault tolerant data storage system comprises an array of memory chips having a plurality of rows and columns, each row of memory chips CO to CN having a spare chip CS. Each chip comprises an array of memory locations some of which may be faulty. When simultaneously writing or reading data via parallel data lines DO-DN to the respective chips, a map MAP identifies any chip having a fault in the addressed location (e.g. in the addressed column) and connects the data line to a good location in the spare chip. The logical addresses for the chips are skewed differently for each other as compared with their physical addresses, such that there are not coincident faults in the different chips e.g. only a single chip in a row has a fault in the columns being simultaneously addressed in the respective chips of that row.
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