Fabrication of dense parallel solder bump connections

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United States of America Patent

PATENT NO 5406701
SERIAL NO

08120675

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Abstract

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A method and product are disclosed in which multiple solder bumps on a first planar surface are guided into engagement with terminals on a second planar surface by means of holes formed (by a photolithographic process) in a dielectric layer, which has been added to the second surface to provide the holes (or sockets) through which the solder bumps (or plugs) extend. The perforated (hole-providing) layer may be formed of one of several materials. The preferred perforated layer material is a photo-definable polyimide, which is hardened by heating after the holes have been formed. Small solder bumps may be formed inside the holes on the second surface, in order to facilitate bonding between the solder bumps on the first surface and the terminals on the second surface.

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Patent Owner(s)

Patent OwnerAddress
APROLASE DEVELOPMENT CO LLC2711 CENTERVILLE ROAD SUITE 400 WILMINGTON DE 19808

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Minahan, Joseph A Simi Valley, CA 7 470
Pepe, Angel A Irvine, CA 5 171
Reinker, David M Rancho Santa Margarita, CA 4 201

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