CMOS process and circuit including zero threshold transistors
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United States of America Patent
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Apr 18, 1995
Grant Date -
N/A
app pub date -
Jun 23, 1992
filing date -
Jun 23, 1992
priority date (Note) -
Expired
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Abstract
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.
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