Importance

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Abstract

A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips, connected to an external bus, memory and peripheral unit, respectively, and a local bus, coupled to the CPU and chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU. The internal bus on the first chip includes a burst mode control line for selected operating units. An operating unit obtaining access to the internal bus and activating its burst mode control line is effective to lock the internal bus for a plurality of operating cycles, during which data is transferred continuously in a burst mode over the internal bus.

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First Claim