Efficient data processor instrumentation for systematic program debugging and development

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United States of America Patent

PATENT NO 5412799
SERIAL NO

08041908

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Abstract

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A program is first analyzed in an ideal environment that assumes infinite processing resources and zero communication latency. In this environment, the program is viewed as being comprised of a plurality of steps of computation. Each step of computation is defined as the set of instructions that have all their operands available at that time. As such, each step of computation is limited only by data dependencies. The number of instructions executed for each step of computation is counted by the data processing system. The count of instructions may be used to produce an ideal parallelism profile that produces a graphical representation of the simulation. Having established an ideal level of parallelism in the ideal environment, a more realistic profile of the maximum level of parallelism may be obtained through analusis that accounts for a finite number of processors and for communication latency. This more realistic simulation is compared to the actual level of parallelism experienced when the program is executed. Should the comparison reveal room for improvement the program is tuned to resolve problems of work distribution and contention. of processors that process tokens; comprising the step of: a) inserting in with other tokens barrier token that causes statistics maintained by the processors to be sampled and available for output; b) processing the other tokens; and c) processing the barrier token to generate the sampling of the statistics.

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Patent Owner(s)

Patent OwnerAddress
MASSACHUSETTS INSTITUTE OF TECHNOLOGYCAMBRIDGE MA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Papadopoulos, Gregory M Arlington, MA 15 964

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