Importance

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Abstract

A serial bit input controller uses clock and data input lines for communicating command information, as well as the clock and data information, to an integrated circuit chip. The circuit functions by employing a multi-stage shift register as a command storage register. The outputs of the shift register are connected to the inputs of coincidence logic gates, the outputs of which in turn supply signals to command state latch circuits. The selection of any one of the command state latch circuits depends upon the data stored in the multi-stage shift register. The shift register, in turn, is enabled by signals on the clock line by holding the clock line high and toggling it with data pulses. When the desired count is reached, the clock signal is allowed to resume, and is applied to the latch circuits to store the command state in the selected latch circuit. To clear the system, a two-stage binary clear latch is employed. This clear latch is enabled by signals on the clock data line when the clock signals is held low. This circuit is toggled by the next data pulse, which causes it to produce a clear output pulse to all of the command state latch circuits.

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First Claim