An interconnection network for interconnection in parallel of a large number (N) of processing elements (PE). The network includes three serial switching stages. The first stage in which the processing elements arc grouped in r clusters of k processing elements each comprising many small fast electronic switches, one for each cluster. The second stage comprises a large number (N) of optical channels, one for each of the N processing elements. The third stage comprises k photodetectors for each of the clusters and electronic switches of the type in the first stage. Each cluster controls k light sources, one for each channel and k photodetectors in the cluster. Interconnection between processing elements in a common cluster are made solely by way of an electronic switch. Interconnection between processing elements in different clusters is made via the optical channels and one or two of the electronic switches.
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