Computerized generation of truth tables for sequential and combinatorial cells

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United States of America Patent

PATENT NO 5416719
SERIAL NO

07991915

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Abstract

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A computerized method of generating a truth table of a cell in a library of circuit cells includes representing basic elements of the cells in a hardware description language, representing each cell as a set of equations in that language and parsing the equations each in accordance with a respective abstract data tree of which the `leaves` or extremities are signal values or constants. The parsing of each equation yields a respective partial truth table. The partial truth tables are merged to provide a complete truth table, which is preferably subjected to Boolean and/or expression optimization to reduce the number of entries in the truth table.

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Patent Owner(s)

Patent OwnerAddress
VLSI TECHNOLOGY INC1109 MCKAY DRIVE SAN JOSE CA 95131

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pribetich, Olivier Vallaurais, FR 8 172

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