Method and apparatus for encoding and decoding convolutional codes
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United States of America Patent
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May 16, 1995
Grant Date -
N/A
app pub date -
Jul 29, 1992
filing date -
Jul 30, 1991
priority date (Note) -
In Force
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Abstract
A reduction of the redundancy due to the use of the convolutional codes as the error correction codes is achieved by a convolutional encoding at an identical encoding rate and a puncture process using different puncture rates for different classes of the input signals classified by the error sensitivity of each bit. A reduction of the decoding delay time without deteriorating the decoding error rate is achieved by updating the survivor path by remaining bits of the selected survivor path for each state other than the oldest bit and an additional bit indicative of the each state to which a transition is made at the present stage of decoding. A reduction of a circuit size of a Viterbi decoder is achieved by using a single RAM for memorizing a path metric and a survivor path for each state at an immediately previous stage of decoding together in each word of the memory capacity. A reduction of the decoding error rate for the data block encoded by the convolutional encoding is achieved by using the (i+N+j) bits of decoder input signals containing entire N bits of the received signals, preceded by last i bits of the received signals and followed by first j bits of the received signals.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| KABUSHIKI KAISHA TOSHIBA | 72-34 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI KANAGAWA 2120013 ?2120013 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Kodama, Tomoko | Kanagawa, JP | 14 | 452 |
| Nakamura, Makoto | Hyougo, JP | 369 | 5498 |
| Saito, Tatsunori | Kanagawa, JP | 22 | 609 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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