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Abstract

A complete logic family which is SEU immune is constructed, using logic/circuit design techniques, to recover from an SEU, regardless of the shape of the upsetting event. The logic family provides a redundancy of data to be used to restore data lost by an SEU. Two transistor networks are used, a p-channel network and an n-channel network. Each transistor network consists of a plurality of input transistors and a feedback transistor. The feedback transistor is sized to be weak compared to the input transistors. The transistor networks are designed to either resist an SEU or to shutdown until the SEU is over and then the network which is not shutdown will restore the data of the network that was hit by the SEU. The logic family can prevent glitch propagation from an upset node and can be implemented in a standard, commercial CMOS process without any additional processing steps. The logic family includes but is not limited to an Inverter, 2-input Nand, 2-input Nor, 3-input OrNand and a 3-input AndNor. The SEU recovery mechanism used by the logic family can be extended to logic structures in general. The SEU recovery mechanism is independent of the duration or shape of the upsetting event.

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First Claim