Semiconductor integrated circuit, method of designing the same and method of manufacturing the same
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United States of America Patent
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May 30, 1995
Grant Date -
N/A
app pub date -
Oct 4, 1993
filing date -
Dec 28, 1992
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.
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