Layout method for a semiconductor integrated circuit device
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United States of America Patent
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May 30, 1995
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N/A
app pub date -
Sep 2, 1994
filing date -
Jun 26, 1990
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Abstract
A method is provided for designing a semiconductor integrated circuit device with optimized shape of blocks to minimize the size of the chip containing the circuit. Design restrictions on the shape and position of each block are determined according to the density of temporary paths for electrical connections between blocks and the shape of each side of each block is optimized within the restrictions. The internal layout of each block is then optimized according to the restrictions.
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