Data processing system having selective data save and address translation mechanism utilizing CPU idle period
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United States of America Patent
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May 30, 1995
Grant Date -
N/A
app pub date -
Apr 25, 1991
filing date -
Apr 27, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A main memory has a plurality of divided storage areas. A central processing unit saves data from each storage area of the main memory into an auxiliary memory during a normal operation of a computer system, and sets a flag corresponding to each storage area, from which the data is saved, in a state indicating the end of a save operation. In addition, when data stored in the main memory is updated, the central processing unit changes the flag into a state indicating an incomplete save state. When the computer system must be stopped, the central processing unit saves data, of the data stored in the main memory, only from a storage area for which the flag indicates an incomplete save state into the auxiliary memory, thereby shortening the time required for save processing.
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