Non-conductive end layer for integrated stack of IC chips
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United States of America Patent
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-
Jun 13, 1995
Issued Date -
N/A
app pub date -
Apr 25, 1994
filing date -
May 15, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.
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