Importance

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Abstract

A data processing system (10) is described which comprises an integrated decoder circuit (12) comprising an input buffer (14) and an error signal generator circuit ( 18 ) . The error signal generator circuit ( 18 ) generates a pulse width modulated error signal output to a clock processing circuit (20). The clock processing circuit (20) may comprise a low pass filter (24) and a variable oscillator (26). The clock processing circuit (20) supplies a clock signal to a digital-to-analog converter (16). The digital-to-analog converter (16) uses the clock signal to correctly track the bit rate for the encoded bit stream received by decoder system (12).

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First Claim