Importance

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Abstract

A microcomputer system providing high performance access to external Special Function Registers (SFRs), has an 8051 architecture microcontroller modified such that the instruction stream can be externally examined and decoded by an external expansion decoder. The instruction stream can be examined and decoded regardless of whether the microcontroller fetches instructions from an internal program memory or an external program memory. Every State 6, Phase 2, data on the internal bus of the modified microcontroller is transferred to the PORT2 pins and is available to the external expansion decoder. During reset the microcontroller latches the state of the EA pin to internally determine whether to operate in ROM or ROMless mode. Thereafter, EA operates as a bi-directional control pin that, as an output, signals whether the current bus cycle is an instruction fetch, and, as an input, signals whether the microcontroller shall read the data present on a certain set of I/O pins in order to complete an SFR read operation. The expansion decoder determines whether the current instruction is one which may operate on an SFR, and if so it further decodes the SFR address associated with the current instruction, and produces appropriate read and write control signals for accessing an external SFR. The expansion decoder may contain either a fixed or programmable table of valid external SFR addresses. External SFR addresses represent peripheral functions, increased data memory or both. The system reduces the number of cycles required to access an external device in an 8051 architecture system by providing access to external devices as if they were architecturally internal devices.

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First Claim