Phase locked loop with low power feedback path and method of operation
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United States of America Patent
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Jun 27, 1995
Grant Date -
N/A
app pub date -
Sep 6, 1994
filing date -
Sep 6, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain 'PLL lock.' However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.
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