Latent defect handling in EEPROM devices
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United States of America Patent
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Jun 27, 1995
Grant Date -
N/A
app pub date -
Sep 21, 1992
filing date -
Sep 21, 1992
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connected respectively to all the sources and drains of each column of cells. The memory system incorporates a word line current detector and an erase line current detector in addition to the usual bit line current detectors. The leakage current of each of the lines are measured after predetermined memory events such as program or erase operations. When a defective row or column is detected, it is electrically isolated from other columns by programming and is mapped out and replaced. Data recovery schemes include reading a defective column by a switched-memory-source-drain technique.
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