Event signalling system and method for processor system having central memory unit
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United States of America Patent
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Jun 27, 1995
Issued Date -
N/A
app pub date -
May 7, 1993
filing date -
May 18, 1990
priority date (Note) -
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Abstract
An event signalling system is provided for a digital signal processor apparatus which has a central data RAM, at least one computing processor, each computing processor having event occurrence circuitry, a plurality of data I/O processors, and a data RAM bus coupled to the data RAM, the computing processor(s) and the I/O processors. The event signalling system includes an address code generating circuit in each data I/O processor for generating different predetermined address codes for each I/O processor and for writing the predetermined address codes onto the data RAM bus upon the occurrence of events of interest. The occurrence of the predetermined address codes on the data RAM bus. are monitored by an address decoder which generates different signals depending upon the predetermined address code found. The signals from the address decoder are carried by a flag bus to the event occurrence circuitry of the computing processor(s), and to the output sections of the I/O processors.
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