Computer system with clock shared between processors executing separate instruction streams
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United States of America Patent
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Jun 27, 1995
Grant Date -
N/A
app pub date -
Mar 21, 1989
filing date -
Mar 23, 1988
priority date (Note) -
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Abstract
A multiprocessor system which includes a control processor and a high-level data-transfer processor. Both of these two processors are docked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.
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