Method and apparatus for disabling and restarting clocks
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United States of America Patent
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Jun 27, 1995
Grant Date -
N/A
app pub date -
Aug 12, 1993
filing date -
Aug 12, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The ability to stop a clock in a CMOS peripheral device or other CMOS IC, and reliably restart it based on an asynchronous event, provides the basis for considerable power savings. In a computer system 20 an interface component 10 has a clock restart circuit 100. The restart circuit 100 includes a series of D-type CMOS flip-flops (110, 112, 118) that are initially set in their zero state. A logic OR gate 120 receives the microprocessor clock and the complimentary output of the last flip-flop to provide a reliable, restarted clock signal for the interface component 10 and its peripherals 26.
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