Error detection scheme in a multiprocessor environment

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United States of America Patent

PATENT NO 5428766
SERIAL NO

07983907

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processor computer system implementing a buffer swapping scheme. The error detection scheme of the present invention provides for the monitoring of bus transactions, maintaining a log of bus activity including buffer access transactions, identifying transactions involving buffer and address recognition operations and checking those operations to insure that they are consistent with the implemented buffer swapping scheme. Upon detection of an error the bus monitoring device asserts an error signal, freezes the log of bus activity and halts buffer swapping activity until the detected error is investigated and dealt with in an appropriate manner.

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Patent Owner(s)

  • ENTERASYS NETWORKS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Seaman, Michael J San Jose, CA 25 2334

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