Method and apparatus for a unified parallel processing architecture

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United States of America Patent

PATENT NO 5428803
SERIAL NO

07912964

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Abstract

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A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP1701 EAST MOSSY OAKS ROAD SPRING TX 77389

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beard, Douglas R Eleva, WI 22 1006
Chen, Steve S Eau Claire, WI 21 2172
Priest, Edward C Eau Claire, WI 12 547
Spix, George A Eau Claire, WI 25 1875
VanDyke, James M Eau Claire, WI 2 86
Wastlick, John M Eau Claire, WI 6 226

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